A Hardware Implementation of a Network of Functional Spiking Neurons with Hebbian Learning

Nowadays, networks of artificial spiking neurons might contain thousands of synapses. Although software solutions offer flexibility, their performance decreases while increasing the number of neurons and synapses. Embedded systems very often require real-time execution, which do not allow an unconstrained increasing of the execution time. On the other hand, hardware solutions, given their inherent parallelism, offer the possibility of adding neurons without increasing the execution time. In this paper we present a functional model of a spiking neuron intended for hardware implementation. Some features of biological spiking neurons are abstracted, while preserving the functionality of the network, in order to define an architecture with low implementation cost in field programmable gate arrays (FPGAs). Adaptation of synaptic weights is implemented with hebbian learning. As an example application we present a frequency discriminator to verify the computing capabilities of a generic network of our neuron model.